Vertical Double-Diffused Metal Oxide Field Effect Transistors (VDMOSFETs) are used because of their high-current, high-voltage capabilities. FIGS. 1a and 1b respectively represent simplified cross-sectional views of a basic design/layout of N-channel and P-Channel VDMOSFETs 1, 3, respectively (a structure is cut parallel to sources along a metal oxide semiconductor (MOS) gate—cut lines are shown as AB in FIGS. 2a and 2b). A VDMOSFET 1 as shown is made of a doped substrate (e.g., N-channel devices use N+ substrates 104; whereas, FIG. 1b shows a P-channel device using P+ substrates 113). A conductive layer contacting bottom of a substrate 104 (for N-channel) or substrate 113 (for P-channel) forms a drain contact 102. At top of substrate 104 or 113 is a lighter-doped epitaxial layer (N-channel devices use N-type silicon 103; referring to FIG. 1b, P-channel devices use P-type silicon 112). In an alternative embodiment (not shown), a second epitaxial layer (referred to as a buffer layer in this example) can be added between layers 103 and 104 (for N-channel) to enhance single-event burnout (SEB) performance. At a surface of the exemplary epitaxial layer 103, a region of opposite doping 105, 105′ is implanted/diffused to form a doped region (hereinafter referred to as body) (e.g., N-channel devices use P-type doping (P-body) 105, 105′ and P-channel devices use N-type doping (N-body) 114, 114′). To ensure good contact between source contact and body, e.g., 101 and 105, a higher doped region, e.g., 106, can be implanted/diffused into the exemplary body (e.g., N-channel device use a higher doped P region 106, 106′ and P-channel devices use a higher doped N region 115, 115′). Once doped regions, e.g., various bodies (e.g., P-body 105, 105′ or N-body 115, 115′) are manufactured, an opposite doping of exemplary body region (e.g., N-body 107, 107′, P-body 116, 116′) can be implanted/diffused to define source regions (e.g., N-channel devices use N-type doping (e.g., N-body) 107 and P-channel devices use P-type doping (P-body) 116). A source contact conductive layer 101 (or FIG. 1b, 101′) can be deposited connecting source and body regions (e.g., P-body 106/N-body 107 or N-body 115/P-body 116) forming a portion of an electrical conductive path (shown as one segment of dashed lines through these areas) for an electrical power supply (not shown). A dielectric material (e.g., a gate oxide 108) can be placed on top of epitaxial region (N type silicon 103) and over/between N source 107 and N source 107′. In FIG. 1a, MOS gate 109 is formed with a conductive layer placed on top of gate oxide 108. A portion of P-Body 105, 105′ (FIG. 1a) respectively between N-Source 107 or 107′ and N Type Silicon epitaxial layer 103 respectively defines semi-conductive channel regions 111, 111′. Referring to FIG. 1b, a portion of N-Body 114, 114′ respectively between P-Source 116 or 116′ and the P Type Silicon epitaxial layer 112 respectively defines semi-conductive channel regions 111″, 111′″. Dashed lines show electrical conductive paths that are formed during operation of FIGS. 1a and 1b VDMOSFETs.
Attempts have been made, including numerous modifications/improvements in the design, layout, and fabrication of vertical power metal oxide semiconductor field effect transistors (MOSFETs) to enhance their electrical and radiation performance (e.g., increase power density, decrease on-resistance, increase radiation hardness, etc.). For example, radiation-tolerant power, MOSFETs were first introduced to address requirements of various military and space applications. Since then, numerous radiation issues have been discovered and significant research has been devoted to resolving specific radiation issues (e.g., total ionizing dose (TID), single-event gate rupture (SEGR), and SEB issues).
Under some types of MOSFET operation, application of an appropriate gate voltage (a gate voltage greater than the device's gate threshold voltage) forms a conducting path between source and drain allowing current to flow (device is turned on). Higher gate voltages equates to higher current flow. One effect of TID is to trap charge in gate oxide, which causes MOS gate threshold voltage to shift (e.g., gate voltage required to turn on the device can change with TID). If this TID-induced shift is sufficiently large, n-channel devices cannot be turned off and become non-functional. When threshold voltage of re-channel device shifts below zero volts and becomes negative (e.g., n-channel devices have positive threshold voltages), that device is said to have failed by going into depletion mode. An exemplary MOS gate threshold voltage shift of p-channel devices has an opposite effect. P-channel devices become impossible to turn-on without applying an excessive gate voltage that can damage device. Methods have been attempted to help resolve TID issues in power MOSFETs. One method seeks to decrease gate oxide thickness (e.g., a thinner gate oxide traps less charge but makes device more susceptible to SEGR). Another method seeks to ensure high quality of final gate oxide by manufacturing radiation-hardened gate oxides but these rad-hard oxides can be expensive and exhibit variability in radiation hardness from processing lot to processing lot. Another method seeks to apply higher gate voltages to turn-on or turn-off the device but threshold voltages can shift beyond a safe operating voltage; higher gate voltages can also make devices more susceptible to SEGR.
FIGS. 3a and 3b represent a simplified cross sectional view of a basic design/layout of N-channel and P-Channel Junction Field Effect Transistors (JFETs), respectively (the exemplary structure is cut parallel to the drain and source and along the JFET gate). Unlike MOSFETs, the JFETs use a reverse biased P-N junction to control current flow by modulating the depletion layer width. The JFET consists of a doped semiconductor layer (N-Channel JFETs use N-Type Substrates 122; whereas, P-Channel JFETs use P-Type Substrates 123). A conductive layer can be deposited onto opposite ends of substrate forming the drain contact 120 and source contact 121 of the JFET. Toward a middle of 122 or 123, a region is implanted/diffused with opposite doping of the substrate (N-Channel JFET uses a P-type Silicon 117; whereas, P-Channel JFETs use N-Type Silicon 119) forming the PN junction. A conductive layer is deposited onto these opposite doped regions to form the gate contact 118.
Unlike MOSFETs, JFETs exhibit a natural hardness to TID radiation. TID issues in MOSFETs are directly related to trapped charge in gate oxide used to modulate conductive channel; whereas, JFETs do not use dielectric materials to form a conductive channel making it naturally hard to TID.
Power MOSFETs subjected to space-like environments or other particle-enriched environments are prone to SEGR and SEB, which can adversely affect the device's performance and may even cause system failure. For SEB, a main area of concern is the interaction of a charged particle with the inherent parasitic bipolar transistor where the source acts like an emitter, the body acts like a base and the drain acts like a collector (e.g., see FIG. 4). For SEGR, the main area of concern is the interaction of a charged particle strike within neck region defined by the epitaxial region under the gate oxide between adjacent body regions (e.g., see FIG. 4). When a charge particle traverses a semiconductor material, it sheds energy in accordance with its linear energy transfer (LET) function for that material and that energy can create electron-hole pairs along particle's path. In presence of an electric field, these electron-hole pairs can separate producing unwanted current flow. A resultant current flow under certain conditions can lead to SEB or SEGR. SEB can occur if this current flow is sufficient to locally turn on the parasitic bipolar transistor which if not interrupted may lead to thermal runaway (device fails catastrophically). SEB mechanisms can be more complex than presented here but the intent is to only provide a cursory explanation of SEB. SEGR can occur if this current flow disrupts the depletion field in the epitaxial layer under the gate and couples a portion of the drain potential across the gate dielectric sufficient to damage gate dielectric (e.g., see FIG. 5). SEGR mechanisms can be more complex than presented here but the intent is to only provide a cursory explanation of SEGR.
Some high-voltage applications involving RF mixers, amplifiers, gain control, and detectors may employ two devices to perform the intended application. If an electrical circuit uses two devices to accomplish the intended application, there can be added costs, more space, and added weight when compared to a single device option.
One exemplary embodiment of the invention, such as a planar Dual-Gate Vertical Double-Diffused Metal Oxide Semiconductor Field Effect Transistor (DGVDMOSFET), can be a layout/design of an innovative structure integrating and combining aspects of improved VDMOSFETs and operational gates of JFETs. Therefore, an exemplary improved DGVDMOSFET has advantages of both VDMOSFETs and JFETs creating an exemplary innovative new device and related methods thereof: the DGVDMOSFET. Presently, dual-gate MOSFETs can be built by packaging two MOSFETs into a hybrid-type package with two MOSFETs placed in series but this implementation does not address radiation issues and increases overall cost, weight and size. Another implementation can be to fabricate two lateral MOSFETs in series using a monolithic type layout. However, use of lateral MOSFETs can limit a drain-to-source blocking voltages of such devices to applications that are typically less than 100V due to surface area considerations (blocking voltage is basically determined by the lateral spacing between drain and source and doping) and does not address radiation issues. Drain-to-source blocking voltage of the VDMOS can be determined by the epitaxial layer thickness and doping; therefore, an exemplary DGVDMOSFET can be fabricated for blocking voltages that exceed 1000V providing a new device for high-voltage applications. This exemplary device can be useful in RF type applications such as mixers, gain control, amplifiers, and detectors.
Exemplary embodiments of the invention, e.g., DGVDMOSFET, can also enhance operational performance in radiation environments, specifically SEB, SEGR, and TID environments. Existing power VDMOSFETs can be prone to catastrophic failure from SEB and SEGR, if operated in radiation environments where particles such as neutrons, protons, and heavy ions are present. An exemplary DGVDMOSFET structure can provide an enhanced barrier (e.g., enhanced depletion region) to reduce interactions of radiation particles with exemplary embodiments of the invention from suffering from SEB and SEGR conditions. Existing power VDMOSFETs can also be prone to TID-induced threshold voltage (VTH) shifts from ionizing radiation environments, which can lead to device failure in their intended application. An exemplary embodiment's independent JFET gate can provide a radiation hardened by design (RHBD) approach to reduce TID effects providing enhanced operational performance beyond an operational failure point of VDMOSFETs (e.g., an exemplary improved JFET gate can allow the exemplary structure to be turned off even after the MOS gate becomes non-functional from TID-induced threshold voltage shifts).
FIG. 6 provides one simplistic application of a dual gate transistor e.g., DGVDMOSFET 200 or 200′, used in a RF mixer circuit. Dual gate transistors can be useful in many types of RF applications.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of the illustrative embodiment(s) exemplifying some best modes of carrying out the invention as presently perceived.